module ad828drive(
input clk_50M,
input reset,
input[9:0] data_in,
output ad_clk,
output[9:0]
data_out );
assign ad_clk = clk_50M;
reg[9:0] data_out_r;
always @(posedge clk_50M or negedge reset)
begin
if(!reset)
begin
data_out_r = 10'b0000000000;
end
else
begin
data_out_r = data_in;
end
end
assign data_out = data_out_r;
endmodule
ADS828是一个10位的并行ADC,时序图在上面。望大神指教。不知道我那样写的对不对。求解救
input clk_50M,
input reset,
input[9:0] data_in,
output ad_clk,
output[9:0]
data_out );
assign ad_clk = clk_50M;
reg[9:0] data_out_r;
always @(posedge clk_50M or negedge reset)
begin
if(!reset)
begin
data_out_r = 10'b0000000000;
end
else
begin
data_out_r = data_in;
end
end
assign data_out = data_out_r;
endmodule
ADS828是一个10位的并行ADC,时序图在上面。望大神指教。不知道我那样写的对不对。求解救